/**
 * \file
 *
 * \brief SAMG55 clock configuration.
 *
 * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
 *
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 *
 * \page License
 *
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 */

#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED

// ===== System Clock (MCK) Source Options
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_XTAL
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_BYPASS
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_8M_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_16M_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_24M_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_XTAL
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_BYPASS
#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLLACK

// ===== System Clock (MCK) Prescaler Options   (Fmck = Fsys / (SYSCLK_PRES))
#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_1
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_2
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_4
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_8
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_16
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_32
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_64
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_3

// ===== PLL0 (A) Options   (Fpll = (Fclk * PLL_mul) / PLL_div)
// Use mul and div effective values here.
#define CONFIG_PLL0_SOURCE          PLL_SRC_SLCK_XTAL
#define CONFIG_PLL0_MUL             3000
#define CONFIG_PLL0_DIV             1

// ===== PLL1 (B) Options   (Fpll = (Fclk * PLL_mul) / PLL_div)
// Use mul and div effective values here.
// Intended frequency for USB is 48MHz
// Source is 32768 Hz crystal oscillator
// 32768 * 1465 = 48.005MHz
#define CONFIG_PLL1_SOURCE          PLL_SRC_SLCK_XTAL
#define CONFIG_PLL1_MUL             1465
#define CONFIG_PLL1_DIV             1

// ===== USB Clock Source Options   (Fusb = FpllX / USB_div)
// Use div effective value here.
//#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL0
#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV           1

// ===== Target frequency (System clock)
// - External XTAL frequency: 32768Hz
// - System clock source: SLCK XTAL
// - System clock prescaler: 1 (divided by 1)
// - PLLA source: SLCK_XTAL
// - PLLA output: SLCK_XTAL *  3000 / 1
// - System clock: SLCK_XTAL *  3000 / 1 = 98.304MHz
// ===== Target frequency (USB Clock)
// - USB clock source: PLLA
// - USB clock divider: 1 (divided by 1)
// - PLLA output: SLCK_XTAL * 1465 / 1
// - USB clock: 32768 * 1465 / 1 / 1 = 48MHz

#define CONFIG_PLL0_FREQ		98304000UL

#endif /* CONF_CLOCK_H_INCLUDED */
